Key points of this article.
Since the pin assignments of the TO-247-4L package with driver source pins and the TO-247N package without driver source pins are different, care needs to be taken when patterning the layout.
When the TO-247-4L is connected to the gate driver, the wiring must cross due to the pin assignment, and it is not possible to configure them on the same surface, so the OUT signal and the GND2 signal will form two loops, and surges will be generated depending on the loop area and its ratio.
As a countermeasure, it is necessary to reduce the loop area as much as possible and make the area of loop (1) and loop (2) equal. In addition, it is necessary to consider adding a basic surge suppression circuit or even a buffer circuit.
In this article, we will discuss considerations related to board layout wiring for TO-247-4L package products with driver source pins. Since the pin assignment of the TO-247-4L is different from that of the conventional package, attention needs to be paid to the layout and wiring.
Precautions for circuit board layout and wiring of TO-247-4L with driver-source pins
The pin assignment of the TO-247-4L with driver-source pins differs from that of the conventional TO-247N, as described in the article "Package with Driver-Source Pins". The pin assignment diagrams for the TO-247N, TO-247-4L with driver source pins, and TO-263-7L are shown here again.
The gate pins of the TO-247-4L are on the far right side facing the stamped surface, while the gate pins of the conventional TO-247N package are on the far left side. MOSFETs are typically driven by driver ICs, but most driver ICs have pin assignments that are appropriate for the conventional TO-247N package. Below is an example of the MOSFET wiring diagram when using ROHM driver IC BM61S40RFV-C.
In the case of the TO-247N, the MOSFET drive signal OUT and Return signal GND2 are arranged in the same order as the gate and source pins, so they can be wired in parallel on the same surface.
In contrast, in the TO-247-4L package, the gate pins and driver source pins are arranged in the opposite order to the driver IC pins, as shown in the figure, and the wiring must cross and cannot be configured on the same face. Therefore, as shown in the figure, the OUT signal and the GND2 signal form two loops, and the area ratio of the loop area (1) and (2) needs to be noted.
Typically, MOSFETs in TO-247-4L packages are used in environments with large dID/dt values. When the flux change (dΦ/dt) caused by its current change is orthogonal to this loop area, an electric potential proportional to the loop area of the driver circuit is generated. And, at certain loop area ratios between the gate and source of the MOSFET, the voltage values sometimes reach levels that may cause problems such as positive surges and negative surges. Therefore, it is necessary to make the loop area formed by the OUT signal and GND2 signal as small as possible and to make the area of loop (1) and loop (2) equal.
The pin assignment of the TO-263-7L package is the same as that of the TO-247N, so two loops like the TO-247-4L cannot be formed, so wiring can be performed using the same method as conventional. However, since ROHM's driver ICs are equipped with GND2 pins on both sides of the drive signal OUT pins (pins 1 and 5), they can be wired using the same method as the conventional package, even in the TO-247-4L package.
Also, the addition of a VGS surge suppression circuit has been suggested in some previous articles, but even so, the VGS surge may still exceed the VGS rating due to ringing at VDS shutdown. In this case, VGS surges can be suppressed within the rated range by reducing the wiring impedance from HVdc or adding anti-surge countermeasures such as buffering circuits to each MOSFET. For how to design a buffer circuit, please refer to the application guide "How to design a buffer circuit".